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rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad7701 lc 2 mos 16-bit a/d converter features monolithic 16-bit adc 0.0015% linearity error on-chip self-calibration circuitry programmable low-pass filter 0.1 hz to 10 hz corner frequency 0 v to +2.5 v or 2.5 v analog input range 4 ksps output data rate flexible serial interface ultralow power applications industrial process control weigh scales portable instrumentation remote data acquisition functional block diagram 14 15 7 64 17 av dd dv dd av ss dv ss sc1 sc2 13 calibration sram 16-bit a/d converter analog modulator cal sleep 11 20 19 clock generator serial interface logic sdata sclk 3 2 1 18 clkin clkout mode drdy 6-pole gaussian low-pass digital filter ad7701 5 dgnd agnd a in v ref 8 9 10 bp/ up 12 16 cs calibration microcontroller general description the ad7701 is a 16-bit adc that uses a sigma-delta conver sion technique. the analog input is continuously sampled by an analog modulator whose mean output duty cycle is proportional to the input signal. the modulator output is processed by an on-chip digital filter with a six-pole gaussian response, which updates the output data register with 16-bit binary words at w ord rates up to 4 khz. the sampling rate, filter corner frequency, and output word rate are set by a master clock input that may be supplied externally, or by a crystal controlled on-chip clock oscillator. the inherent linearity of the adc is excellent and endpoint accuracy is ensured by self-calibration of zero and full scale, which may be initiated at any time. the self-calibration scheme can also be extended to null system offset and gain errors in the input channel. the output data is accessed through a flexible serial port, which has an asynchronous mode compatible with uarts and two synchronous modes suitable for interfacing to shift registers or the serial ports of industry-standard microcontrollers. cmos construction ensures low power dissipation, and a power- down mode reduces the idle power consumption to only 10 w. product highlights 1. the ad7701 offers 16-bit resolution coupled with outstand- ing 0.0015% accuracy. 2. no missing codes ensures true, usable, 16-bit dynamic range, removing the need for programmable gain and level-setting circuitry. 3. the effects of temperature drift are eliminated by on-chip self-calibration, which removes zero and gain error. external circuits can also be included in the calibration loop to remove system offsets and gain errors. 4. a flexible synchronous/asynchronous interface allows the ad7701 to interface directly to uarts or to the serial ports of industry-standard microcontrollers. 5. low operating power consumption and an ultralow power standby mode make the ad7701 ideal for loop-powered remote sensing applications, or battery-powered portable instruments.
ad7701* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. documentation application notes ? an-368: evaluation board for the ad7701/ad7703 sigma- delta adcs ? an-375: adm2xxl family for rs-232 communications ? an-607: selecting a low bandwidth (<15 ksps) sigma- delta adc data sheet ? ad7701: lc 2 mos 16-bit a/d converter data sheet tools and simulations ? sigma-delta adc tutorial reference materials technical articles ? delta-sigma rocks rf, as adc designers jump on jitter ? ms-2210: designing power supplies for high speed adc design resources ? ad7701 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7701 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
rev. e ? ad7701?pecifications parameter a, s version 2 b, t version 2 unit test conditions/comments static performance resolution 16 16 bits integral nonlinearity t min to t max 0.0007 % fsr typ 0.003 0.0015 % fsr max differential nonlinearity t min to t max 0.125 0.125 lsb typ guaranteed no missing codes 0.5 0.5 lsb max positive full-scale error 3 0.13 0.13 lsb typ 0.5 0.5 lsb max full-scale drift 4 1.2 ( 2.3 s version) 1.2 ( 2.3 t version) lsb typ unipolar offset error 3 0.25 0.25 lsb typ 1 1 lsb max unipolar offset drift 4 1.6 (+3/?5 s version) 1.6 (+3/?5 t version) lsb typ bipolar zero error 3 0.25 0.25 lsb typ 1 1 lsb max bipolar zero drift 4 0.8 (+1.5/?2.5 s version) 0.8 (+1.5/?2.5 t version) lsb typ bipolar negative full-scale error 3 0.5 0.5 lsb typ 2 2 lsb max bipolar negative full-scale drift 4 0.6 ( 1.2 s version) 0.6 ( 1.2 t version) lsb typ noise (referred to output) 0.1 0.1 lsb rms typ dynamic performance sampling frequency, f s f clkin /256 f clkin /256 hz output update rate, f out f clkin /1024 f clkin /1024 hz filter corner frequency, f ? db f clkin /409,600 f clkin /409,600 hz settling time to 0.0007% fs 507904/f clkin 507904/f clkin sec for full-scale input step system calibration applies to unipolar and positive full-scale overrange v ref + 0.1 v ref + 0.1 v max bipolar ranges. after cali- positive full-scale overrange v ref + 0.1 v ref + 0.1 v max bration, if a in > v ref , the negative full-scale overrange ?v ref + 0.1) ?v ref + 0.1) v max device will output all 1s. maximum offset calibration range 5, 6 if a in < 0 (unipolar) or unipolar input range ?v ref + 0.1) ?v ref + 0.1) v max ? ref (bipolar), the device bipolar input range ?.4 v ref to +0.4 v ref ?.4 v ref to +0.4 v ref v max will output all 0s. input span 7 0.8 v ref 0.8 v ref v min 2 v ref + 0.2 2 v ref + 0.2 v max analog input unipolar input range 0 to 2.5 0 to 2.5 v bipolar input range 2.5 2.5 v input capacitance 10 10 pf typ input bias current 1 11 na typ logic inputs all inputs except clkin v inl , input low voltage 0.8 0.8 v max v inh , input high voltage 2.0 2.0 v min clkin v inl , input low voltage 0.8 0.8 v max v inh , input high voltage 3.5 3.5 v min i in , input current 10 10 a max logic outputs v ol , output low voltage 0.4 0.4 v max i sink = 1.6 ma v oh , output high voltage dv dd ?1 dv dd ?1 v min i source = 100 a floating state leakage current 10 10 a max floating state output capacitance 9 9 pf typ (t a = 25 c; av dd = dv dd = +5 v; av ss = dv ss = ? v; v ref = +2.5 v; f clkin = 4.096 mhz; bipolar mode: mode = +5 v; a in source resistance = 1k 1 with 1 nf to agnd at a in ; unless otherwise noted.)
rev. e ad7701 ? parameter a, s version 2 b, t version 2 unit test conditions/comments power requirements 8 power supply voltages analog positive supply (av dd ) 4.5/5.5 4.5/5.5 v min/v max digital positive supply (dv dd ) 4.5/av dd 4.5/av dd v min/v max analog negative supply (av ss ) ?.5/?.5 ?.5/?.5 v min/v max digital negative supply (dv ss ) ?.5/?.5 ?.5/?.5 v min/v max calibration memory retention power supply voltage 2.0 2.0 v min dc power supply currents 8 analog positive supply (ai dd ) 2.7 2.7 ma max typically 2 ma digital positive supply (di dd )2 2 ma max typically 1 ma analog negative supply (ai ss ) 2.7 2.7 ma max typically 2 ma digital negative supply (di ss ) 0.1 0.1 ma max typically 0.03 ma power supply rejection 9 positive supplies 70 70 db typ negative supplies 75 75 db typ power dissipation normal operation 37 37 mw max sleep l s s sleep l es c cs c c cr u re u u re cs psrr cl s
rev. e ? ad7701 absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6 v dv dd to av dd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v dv ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ? v av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6 v av ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ? v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v digital input voltage to dgnd . . . . ?.3 v to dv dd + 0.3 v analog input voltage to agnd . . . . . . . . av ss ?0.3 v to av dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature range commercial plastic (a, b versions) . . . . . ?0 c to +85 c industrial cerdip (a, b versions) . . . . . . ?0 c to +85 c extended cerdip (s, t versions) . . . . . ?5 c to +125 c storage temperature range. . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . . 300 c power dissipation (any package) to 75 c . . . . . . . . . 450 mw derates above 75 c by . . . . . . . . . . . . . . . . . . . . . 10 mw/ c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. pdip, cerdip, soic mode sc1 dgnd clkout clkin a gnd dv ss av ss a in v ref sdata sclk sc2 cal av dd dv dd drdy cs bp / up sleep top view (not to scale) ad7701 1 2 3 4 5 6 7 8 9 10 14 13 12 11 20 19 18 17 16 15 ssop mode sc1 dgnd clkout clkin a gnd dv ss av ss a in v ref sdata sclk sc2 cal av dd dv dd drdy cs bp / up sleep top view (not to scale) ad7701 1 2 3 4 5 6 7 8 9 10 14 13 12 11 20 19 18 17 16 15 21 22 23 24 25 26 27 28 nc nc nc nc nc nc nc nc nc = no connect pin configurations caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7701 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature linearity package model range error (% fsr) options * ad7701an e40 c to +85 c 0.003 n-20 ad7701bn e40 c to +85 c 0.0015 n-20 ad7701ar e40 c to +85 c 0.003 r-20 ad7701br e40 c to +85 c 0.0015 r-20 ad7701ars e40 c to +85 c 0.003 rs-28 ad7701aq e40 c to +85 c 0.003 q-20 ad7701bq e40 c to +85 c 0.0015 q-20 ad7701sq e55 c to +125 c 0.003 q-20 ad7701tq e55 c to +125 c 0.0015 q-20 * n = pdip; q = cerdip; r = soic; rs = ssop.
rev. e ad7701 ? pin function descriptions pin no. pdip, cerdip, soic ssop mnemonic description 11 mode selects the serial interface mode. if mode is tied to ? v, the ad7701 will operate in the asynchronous communications (ac) mode. the sclk pin is configured as an input, and data is transmitted in two bytes, each with one start bit and two stop bits. if mode is tied to dgnd, the synchronous external clocking (sec) mode is selected. sclk is configured as an input, and the output appears without formatting, the msb coming first. if mode is tied to +5 v, the ad7701 operates in the synchronous self-clocking (ssc) mode. sclk is configured as an output, with a clock frequency of f clkln /4 and 25% duty cycle. 22 clkout clock output to generate an internal master clock by connecting a crystal between clkout and clkin. if an external clock is used, clkout is not connected. 33 clkin clock input for external clock. 4, 17 4, 25 sc1, sc2 system calibration pins. the state of these pins, when cal is taken high, determines the type of calibration performed. 55 dgnd digital ground. ground reference for all digital signals. 68 dv ss digital negative supply, ? v nominal. 6, 7, 9, 11, nc no connect. 18, 21, 22, 23 710 av ss analog negative supply, ? v nominal. 81 2 agnd analog ground. ground reference for all analog signals. 913 a in analog input. 10 14 v ref voltage reference input, 2.5 v nominal. this determines the value of positive full scale in the unipolar mode and of both positive and negative full scale in bipolar mode. 11 15 sleep spd p up upd d re pd re cl cpcld clcl d dd ps d dd dps cs cs cs d de drdy dr drdy scl scscl de ssc cl sd sdd de
rev. e ? ad7701 timing characteristics 1, 2 (av dd = dv dd = +5 v 10%; av ss = dv ss = ? v 10%; agnd = dgnd = o v; f clkin = 4.096 mhz; input levels: logic o = o v, logic 1 = dv dd ; unless otherwise noted.) limit at t min , t max limit at t min , t max parameter (a, b versions) (s, t versions) unit conditions/comments f clkin 3, 4 200 200 khz min master clock frequency: internal gate oscillator. 55 mhz max typically 4.096 mhz. 200 200 khz min master clock frequency: externally supplied. 55 mhz max t r 5 50 50 ns max digital output rise time. typically 20 ns. t f 5 50 50 ns max digital output fall time. typically 20 ns. t 1 00 ns min sc1, sc2 to cal high setup time. t 2 50 50 ns min sc1, sc2 hold time after cal goes high. t 3 6 1000 1000 ns min sleep cls sscde cl cl d cs ld scledd sds sclp scllp cl cl sclred cl cl cl cs d secde scl sc sclp scllp d cs ld scledd cs d scled cde cs s dd scled es s c s clcldsleep d cl s d sleep c cs sdscl cs drdy cs drdy clsd cs scl cl cs sdscl s
rev. e ad7701 ? 1.6ma 200? c l 100pf to output pin i oh 2.1v + i ol figure 1. load circuit for access time and bus relinquish time data va l i d t 10 hi-z sdata cs figure 3. ssc mode data hold time cal sc1, sc2 sc1, sc2 valid t 1 t 2 figure 2a. calibration control timing data va l i d t 15 hi-z sdata cs figure 4a. sec mode data hold time clkin sleep t 3 figure 2b. sleep mode timing hi-z db15 db14 db1 db0 hi-z sdata drdy cs t 12 t 11 t 13 t 14 sclk t 16 figure 4b. sec mode timing diagram hi-z db15 db14 db1 db0 hi-z sclk sdata clkin cs hi-z t 7 t 6 t 5 t 4 t 8 t 5 figure 5. ssc mode timing diagram hi-z start db8 db9 db7 stop 1 stop 2 hi-z high byte low byte sdata sclk drdy cs t 17 t 18 t 19 figure 6. ac mode timing diagram definition of terms linearity error this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 lsb below the first code transition (000 . . . 000 to 000 . . . 001) and full scale, a point 1.5 lsb above the last code transition (111 . . . 110 to 111 . . . 111). the error is expressed as a percentage of full scale. differential linearity error this is the difference between any code? actual width and the ideal (1 lsb) width. differential linearity error is expressed in lsbs. a differential linearity specification of 1 lsb or less guarantees monotonicity. positive full-scale error positive full-scale error is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal (v ref 3/2 lsbs). it applies to both positive and negative analog input ranges and is expressed in microvolts. unipolar offset error unipolar offset error is the deviation of the first code transition from the ideal (agnd + 0.5 lsb) when operating in the uni- polar mode. it is expressed in microvolts. bipolar zero error this is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal (agnd ?0.5 lsb) when operating in the bipolar mode. it is expressed in microvolts. bipolar negative full-scale error this is the deviation of the first code transition from the ideal (? ref + 0.5 lsb) when operating in the bipolar mode. it is expressed in microvolts. positive full-scale overrange positive full-scale overrange is the amount of overhead available to handle input voltages greater than +v ref (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without introducing errors due to overloading the analog modulator or overflowing the digital filter. it is expressed in millivolts. negative full-scale overrange this is the amount of overhead available to handle voltages below ? ref without overloading the analog modulator or overflowing the digital filter. note that the analog input will accept negative voltage peaks even in the unipolar mode. the overhead is expressed in millivolts.
rev. e ? ad7701 offset calibration range in the system calibration modes (sc2 low), the ad7701 cali- brates its offset with respect to the a in pin. the offset calibration range specification defines the range of voltages, expressed as a percentage of v ref , that the ad7701 can accept and still accu- rately calibrate offset. full-scale calibration range this is the range of voltages that the ad7701 can accept in the system calibration mode and still correctly calibrate full scale. input span in system calibration schemes, two voltages applied in sequence to the ad7701? analog input define the analog input range. the input span specification defines the minimum and maxi- mum input voltages from zero to full scale that the ad7701 can accept and still accurately calibrate gain. the input span is expressed as a percentage of v ref. general description the ad7701 is a 16-bit a/d converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those representing chemical, physical, or biological processes. it contains a charge-balancing (sigma-delta) adc, calibration microcontroller with on-chip static ram, clock oscillator, and serial communications port. the analog input signal to the ad7701 is continuously sampled at a rate determined by the frequency of the master clock, clkin. a charge-balancing a/d converter (sigma-delta modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. a six-pole gaussian digi- tal low-pass filter processes the output of the modulator and updates the 16-bit output register at a 4 khz rate. the output data can be read from the serial port randomly or periodically at any rate up to 4 khz. ad7701 mode sdata dgnd clkout clkin a gnd sclk sc2 cal cs bp/ up dv ss dv dd sleep range select calibrate analog input analog ground ?v analog supply 0.1? +5v analog supply 2.5v 0.1? 0.1? vo ltag e reference drdy 0.1? 10? av dd v ref a in av ss 0.1? 10? read ready read (transmit) serial clock serial data figure 7. typical system connection diagram the ad7701 can perform self-calibration using the on-chip calibration microcontroller and sram to store calibration parameters. a calibration cycle may be initiated at any time using the cal control input. other system components may also be included in the calibra- tion loop to remove offset and gain errors in the input channel. for battery operation, the ad7701 also offers a standby mode that reduces idle power consumption to typically 10 w. theory of operation the general block diagram of a sigma-delta adc is shown in figure 8. it contains the following elements: 1. a sample-hold amplifier 2. a differential amplifier or subtracter 3. an analog low-pass filter 4. a 1-bit a/d converter (comparator) 5. a 1-bit dac 6. a digital low-pass filter in operation, the analog signal sample is fed to the subtracter, along with the output of the 1-bit dac. the filtered difference signal is fed to the comparator, whose output samples the differ- ence signal at a frequency many times that of the analog signal sampling frequency (oversampling). analog low-pass filter comparator digital data s/h amp dac digital filter figure 8. general sigma-delta adc oversampling is fundamental to the operation of sigma-delta adcs. using the quantization noise formula for an adc: snr = ( 6 .02 number of bits + 1.76) db a 1-bit adc or comparator yields an snr of 7.78 db. the ad7701 samples the input signal at 16 khz, which spreads the quantization noise from 0 khz to 8 khz. since the specified analog input bandwidth of the ad7701 is only 0 hz to 10 hz, the noise energy in this bandwidth would be only 1/800 of the total quantization noise, even if the noise energy were spread evenly throughout the spectrum. it is reduced still further by analog filtering in the modulator loop, which shapes the quanti- zation noise spectrum to move most of the noise energy to frequencies above 10 hz. the snr performance in the 0 hz to 10 hz range is conditioned to the 16-bit level in this fashion. the output of the comparator provides the digital input for the 1-bit dac, so the system functions as a negative feedback loop that minimizes the difference signal. the digital data that repre- sents the analog input voltage is in the duty cycle of the pulse train appearing at the output of the comparator. it can be re trieved as a parallel binary data-word using a digital filter. sigma-delta adcs are generally described by the order of the analog low-pass filter. a simple example of a first-order, sigma- delta adc is shown in figure 9. this contains only a first-order, low-pass filter or integrator. it also illustrates the derivation of the alternative name for these devices: charge-balancing adcs.
rev. e ad7701 ? c r r a in integrator to digital filter clock 1-bit dac strobed comparator +v ref ? ref figure 9. sec basic charge-balancing adc the term charge-balancing comes from the fact that this system is a negative feedback loop that tries to keep the net charge on the integrator capacitor at zero by balancing charge injected by the input voltage with charge injected by the 1-bit dac. when the analog input is zero the only contribution to the integrator output comes from the 1-bit dac. for the net charge on the integrator capacitor to be zero, the dac output must spend half its time at +1 v and half its time at ? v. assuming ideal com- ponents, the duty cycle of the comparator will be 50%. when a positive analog input is applied, the output of the 1-bit dac must spend a larger proportion of the time at +1 v, so the duty cycle of the comparator increases. when a negative input voltage is applied, the duty cycle decreases. the ad7701 uses a second-order, sigma-delta modulator and a sophisticated digital filter that provides a rolling average of the sampled output. after power-up or if there is a step change in the input voltage, there is a settling time that must elapse before valid data is obtained. digital filtering the ad7701? digital filter behaves like an analog filter, with a few minor differences. first, since digital filtering occurs after the analog-to-digital conversion, it can remove noise injected during the conversion process. analog filtering cannot do this. on the other hand, analog filtering can remove noise super- imposed on the analog signal before it reaches the adc. digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. to alleviate this problem, the ad7701 has over- range headroom built into the sigma-delta modulator and digital filter that allows overrange excursions of 100 mv. if noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the gain in the input channel so that a full-scale input (2.5 v) gives only a half-scale input to the ad7701 (1.25 v). this will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by one bit (50%). filter characteristics the cutoff frequency of the digital filter is f clk /409600. at the maximum clock frequency of 4.096 mhz, the cutoff frequency of the filter is 10 hz and the output rate is 4 khz. figure 10 shows the filter frequency response. this is a six-pole gaussian response that provides 55 db of 60 hz rejection for a 10 hz cutoff frequency. if the clock frequency is halved to give a 5 hz cutoff, 60 hz rejection is better than 90 db. a normalized s-domain pole-zero plot of the filter is shown in figure 11. the response of the filter is defined by: hx xx x xx x () = +++ + ++ ? 10 693 0 240 0 0555 0 00962 0 00133 0 000154 24 6 810 12 05 ... .. . . where xff f f db db clkin == 33 409600 , and f is the frequency of interest. f clk = 2mhz f clk = 1mhz f clk = 4mhz 1 10 100 frequency e hz 20 0 e20 e40 e60 e80 e100 e120 e140 e160 gain e dbs figure 10. frequency response of ad7701 filter jw s 0 j1 j2 ? ? ?1 ?2 s1,2 = ?.4663 + j1.8191 s3,4 = ?.7553 + j1.0005 s5,6 = ?.8739 + j0.32272 figure 11. normalized pole-zero plot of ad7701 filter since the ad7701 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs, and data will be invalid after a step change until the settling time has elapsed. the ad7701 is, therefore, unsuitable for high speed multiplexing, where channels are switched and converted sequen tially at high rates, as switching between chan- nels can cause a step change in the input. rather, it is intended for distributed converter systems using one adc per channel. however, slow multiplexing of the ad7701 is possible, pro- vided that the settling time is allowed to elapse before data for the new channel is accessed.
rev. e ?0 ad7701 the output settling of the ad7701 in response to a step input change is shown in figure 12. the gaussian response has fast settling with no overshoot, and the worst-case settling time to 0.0007% ( 0.5 lsb) is 125 ms with a 4.096 mhz master clock frequency. percent of final value 100 80 60 40 20 0 04080 120 160 time ?ms figure 12. ad7701 step response using the ad7701 system design considerations the ad7701 operates differently from successive approxima- tion adcs or other integrating adcs. since it samples the signal continuously, like a tracking adc, there is no need for a start convert command. the 16-bit output register is updated at a 4 khz rate, and the output can be read at any time, either synchronously or asynchronously. clocking the ad7701 requires a master clock input, which may be an external ttl/cmos compatible clock signal applied to the clkin pin (clkout not used). alternatively, a crystal of the correct frequency can be connected between clkin and clkout, when the clock circuit will function as a crystal controlled oscillator. the input sampling frequency, output data rate, filter character- istics, and calibration time are all directly related to the master clock frequency, f clkin , by the ratios given in the specification table. therefore, the first step in system design with the ad 7701 is to select a master clock frequency suitable for the bandwidth and output data rate required by the application. analog input ranges the ad7701 performs conversion relative to an externally supplied reference voltage that allows easy interfacing to ratiometric systems. in addition, either unipolar or bipolar input voltage ranges may be selected using the bp/ up p up re p up re re u r u ls s s ls s s c u r r sd sd d re ls re ls re ls re ls re ls re ls re ls dls re ls dls re ls dls dls re ls dls re ls dls re ls es re d uls ls
rev. e ad7701 ?1 input signal conditioning reference voltages from 1 v to 3 v may be used with the ad 7701 with little degradation in performance. input ranges that cannot be accommodated by this range of reference voltages may be achieved by input signal conditioning. this may take the form of gain to accommodate a smaller signal range, or passive at tenua- tion to reduce a larger input voltage range. source resistance if passive attenuators are used in front of the ad7701, care must be taken to ensure that the source impedance is sufficiently low. the ad7701 has an analog input with over 1 g dc input resistance. in parallel with this, there is a small dynamic load that varies with the clock frequency (see figure 13). each time the analog input is sampled, a 10 pf capacitor draws a charge packet of maximum 1 pc (10 pf 100 mv) from the analog source a in r1 r2 c ext a gnd ad7701 v os 100mv c in 10pf figure 13. equivalent input circuit and input attenuator with a frequency f clkin /256. for a 4.096 mhz clkin, this yields an average current draw of 16 na. after each sample, the ad7701 allows 62 clock periods for the input voltage to settle. the equation that defines settling time is: vv e oin trc =? [] ? 1 where v o is the final settled value. v in is the value of the input signal. r is the value of the input source resistance. c is the 10 pf sample capacitor. t is equal to 62/f clkin . from this, the following equation can be developed, which gives the maximum allowable source resistance, r s(max) , for an error of v e : r s ( max ) = 62 f clkin (10 pf ) ln ( 100 mv / v e ) provided the source resistance is less than this value, the analog input will settle within the desired error band in the requisite 62 clock periods. insufficient settling leads to offset errors. these can be calibrated in system calibration schemes. if a limit of 10 v (0.25 lsb at 16 bits) is set for the maximum offset voltage, then the maximum allowable source resistance is 160 k from the above equation, assuming that there is no external stray capacitance. an rc filter may be added in front of the ad7701 to reduce high frequency noise. with an external capacitor added from a in to agnd, the following equation will specify the maximum allowable source resistance: r s ( max ) = 62 f clkin ( c in + c ext ) ln 100 mv c in /( c in + c ext ) v e the practical limit to the maximum value of source resistance is thermal (johnson) noise. a practical resistor may be modeled as an ideal (noiseless) resistor in series with a noise voltage source or in parallel with a noise current source: v ktrf volts n = 4 i ktrf r amperes n = 4 where k is boltzmann?s constant (1.38 10 e23 j/k). t is temperature in degrees kelvin ( c + 273). active signal conditioning circuits such as op amps generally do not suffer from problems of high source impedance. their open- loop output resistance is normally only tens of ohms and, in any case, most modern general-purpose op amps have sufficiently fast closed-loop settling time for this not to be a problem. offset voltage in op amps can be eliminated in a system calibration routine. with the wide dynamic range and small lsb size of the ad7701, noise can also be a problem, but the digital filter will reject most broadband noise above its cutoff frequency. how- ever, in certain applications there may be a need for analog input filtering. antialias considerations the digital filter of the ad7701 does not provide any rejection at integer multiples of the sampling frequency (nf clkln /256, where n = 1, 2, 3 . . . ). with a 4.096 mhz master clock, there are narrow ( 10 hz) bands at 16 khz, 32 khz, 48 khz, and so on, where noise passes unattenuated to the output. however, due to the ad7701?s high oversampling ratio of 800 (16 khz to 20 hz), these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. the reduc- tion in broadband noise is given by: e out = e in 2 f c / f s = 0. 035 e in where e ln and e out are rms noise terms referred to the input. f c is the filter e3 db corner frequency (f clkin /409600). f s is the sampling frequency (f clkin /256). since the ratio of f s to f clkin is fixed, the digital filter reduces broadband white noise by 96.5% independent of the master clock frequency.
rev. e ?2 ad7701 voltage reference connections the voltage applied to the v ref pin defines the analog input range. the specified reference voltage is 2.5 v, but the ad7701 will operate with reference voltages from 1 v to 3 v with little degradation in performance. the reference input presents exactly the same dynamic load as the analog input, but in the case of the reference input, source resistance and long settling time introduce gain errors rather than offset errors. fortunately, most precision references have sufficiently low output impedance and wide enough bandwidth to settle to 10 v within 62 clock cycles. a gnd ad7701 +5v av dd v ref lt 1019 figure 14. typical external reference connections the digital filter of the ad7701 removes noise from the refer- ence input, just as it does with noise at the analog input, and the same limitations apply regarding lack of noise rejection at inte- ger multiples of the sampling frequency. if reference noise is a problem, some voltage references offer noise reduction schemes using an external capacitor. alternatively, a simple rc filter may be used, as shown in figure 15. +5v ad580 a gnd ad7701 av dd v ref r f 13k figure 15. filtered reference input the same considerations apply to this filter as to a filter at the analog input. in this case: [ r f ( c f + 10 pf )] = 62 f clkin ln 100 mv c in ( c in + c f ) v fse where f clkin is the master clock frequency. v fse is the maximum desired error in volts. grounding and supply decoupling agnd is the ground reference voltage for the ad7701 and is completely independent of dgnd. any noise riding on the agnd input with respect to the system analog ground will cause conversion errors. agnd should, therefore, be used as the system ground and also as the ground for the analog input and reference voltage. the analog and digital power supplies to the ad7701 are inde- pendent and separately pinned out to minimize coupling between analog and digital sections of the device. the digital filter will provide rejections of broadband noise on the power supplies, except at integer multiples of the sampling frequency. t herefore, the two analog supplies should be decoupled to agnd using 100 nf ceramic capacitors to provide power supply noise rejec- tions at these frequencies. the two digital supplies should sim ilarly be decoupled to dgnd. accuracy and autocalibration sigma-delta adcs, like vfcs and other integrating adcs, do not contain any source of nonmonotonicity and inherently offer no-missing-codes performance. the ad7701 achieves excellent linearity ( 0.0007%) by the use of high quality, on-chip silicon dioxide capacitors, which have a very low capacitance/voltage coefficient. the ad7701 offers two self-calibration modes using the on-chip calibration microcontroller and sram. table iii is a truth table for the calibration control inputs sc1 and sc2. in the self-calibration mode, zero scale is calibrated against the agnd pin and full scale is calibrated against the v ref pin, to remove internal errors. note that in the bipolar mode the ad7701 calibrates positive full scale and midscale (bipolar zero). in the system-calibration mode, the ad7701 calibrates its zero and full scale to voltages present on the analog input pin in two sequential steps. this allows system offsets and/or gain errors to be nulled out. system ref hi a in system ref lo analog mux a0 a1 signal conditioning ad7701 sclk sdata cal sc1 sc2 micro- computer figure 16. typical connections for system calibration a typical system calibration scheme is shown in figure 16. in normal operation, the analog signal is fed to the ad7701 via an analog multiplexer. when the system is to be calibrated, a in is first switched to the system ref lo via the multiplexer and cal is strobed high, with sc1 and sc2 both high. a in is then switched to the system ref hi and cal is strobed, with sc1 low and sc2 high. in this way, the effect of all error sources
rev. e ad7701 ?3 table iii. calibration truth table * cal sc1 sc2 calibration type zero reference fs reference sequence calibration time 00 self-calibration agnd v ref one step 3,145,655 clock cycles 11 system offset a in first step 1,052,599 clock cycles 01 system gain a in second step 1,068,813 clock cycles 10 system offset a in v ref one step 2,117,389 clock cycles * drdy sc drdy d drdy d d d scsc rel d re s u d re d rel d rel relre clrre d re re perupdclr cl cl s cl scsc d persupplyseuec d dd dd p d re dd d dd d dd rud dd re d d slesupplyper d ddd
rev. e ?4 ad7701 a gnd ad7701 av dd v ref 10k figure 17. single-supply operation sleep mode the low power standby mode is initiated by taking the sleep dlerce d sscssc sscde ssc cc sscd d e cs scl sls drdy sd cs sdscl cs drdy ssc d sclscl lsel dlcpu scl sd s ls drdy dlcpu cs plled cs erl sus clcycles clcycles clcycles clcycles figure 18. timing diagram for ssc data transmission mode
rev. e ad7701 ?5 synchronous external clock mode (sec) the sec mode (mode pin grounded) is designed for direct interface to the synchronous serial ports of industry-standard microprocessors such as the cops series, 68hc11, and 68hc05. the sec mode also allows customized interfaces, using i/o port pins, to microprocessors that do not have a direct fit with the ad7701? other modes. as shown in figure 20, a falling edge on cs ss scl ls drdy sd cs d cs s d scl cs d cs drdy cl drdy sd ds d d d dls scl cs cl cycles figure 19. ssc mode showing data timing relative to sclk sclk (i) sdata (o) db15 ( msb) db14 db13 db1 db0 ( lsb) hi-z hi-z drdy (o) cs (i) figure 20. timing diagram for the sec mode
rev. e ?6 ad7701 asynchronous communications (ac) mode the ac mode (mode pin tied to ? v) offers a uart com- patible interface that allows the ad7701 to transmit data asynchronously from remote locations. an external sclk sets the baud rate and data is transmitted in two bytes in uart compatible format. using the ac mode, the ad7701 can be interfaced directly to microprocessors with uart interfaces, such as the 8051 and tms70x2. data transmission is initiated by cs cs scld dd sd cs dd urd cs cs d ur c dlsedupuld d ssc secc cs c sd c secd cl scl sd d sr d d d sp d d d d sp sr sp sp drdy cs figure 21. timing diagram for asynchronous communications mode
rev. e ad7701 ?7 outline dimensions 20-lead plastic dual in-line package [pdip] (n-20) dimensions shown in inches and (millimeters) 20 1 10 11 0.985 (25.02) 0.965 (24.51) 0.945 (24.00) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) bsc 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095-ae 20-lead standard small outline package [soic] wide body (r-20) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ac 0.75 (0.0295) 0.25 (0.0098) 20 11 10 1 0.32 (0.0126) 0.23 (0.0091) 8
rev. e ?8 ad7701 revision history location page 3/03?ata sheet changed from rev. d to rev. e. updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
?9
c0116203/03(e) printed in u.s.a. ?0

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